Building High Performance FIR Filters Using KCM’s
Ken Chapman · 1996
The implementation of digital filters with sample rates above just a few mega-Hertz are generally difficult and expensive to realise using standard digital signal processors. At this point the potential of distributed arithmetic and parallel processing performed in a Xilinx FPGA becomes the ideal solution. The re-programmable aspect of FPGA’s permits optimum use of the available gates in the form of Constant (K) Coefficient Multipliers (KCM), whilst enabling the filter to be tuned or changed at any time. Filters employing fully parallel KCM’s are ideal for sample rates exceeding 27 MHz with the following example able to operate above 50 MHz.