Transistor count and chip-space estimation of simplescalar-based microprocessor model
Marc Steinhaus, Reiner Kolla, Josep-L. Larriba-Pey, Theo Ungerer, Mateo Valero Cortés · UPCommons institutional repository (Universitat Politècnica de Catalunya) · 2001
This paper proposes a chip space and transistor count estimation tool, which receives its input from the baseline architecture and the configuration file of the microarchitecture performance simulator sim-outorder of the SimpleScalar Tool Set. The estimation tool yields a pre-silicon chip space and transistor count estimation and allows to compare different microprocessor configurations with respect to their potential chip space requirements. The estimation method, which is the basis of our tool, is validated by configuration parameters of a real processor yielding a transistor count and a chip space estimation that is very close to the real processor numbers.