CASE-STUDY OF A XILINX SYSTEM GENERATOR DESIGN FLOW FOR RAPID DEVELOPMENT OF SDR WAVEFORMS
David Haessig, Jim Hwang, Sean Gallagher · 2005
ABSTRACT This paper describes a case study examining two distinct design processes for implementation of FPGA-based software defined radio subsystems. We compare a traditional RTL design approach with a model-based design flow involving automatic code generation using System Generator. Both design processes were applied to the development of a common SATCOM waveform: Mil-Std-188-165a. Results indicate a 10:1 improvement in development efficiency using System Generator, based on quantitative comparison of the time consumed in developing system simulations, algorithm documentation, code design and debugging, hardware implementation, and algorithm verification. The time savings associated with performance analysis using hardware co-simulation is also assessed. 1. INTRODUCTION FPGAs have become widely used in the design of physical layer and baseband processing for software-defined radios. However, prevailing programming models, derived from design flows used to design ASICs, have traditionally limited accessibility of FPGA-based signal processing subsystems to designers with a background in chip design. This situation has been changing over the last five years with the emergence of a new class of FPGA programming flows based on high level modeling in MATLAB and Simulink. The Xilinx