Integrated JTAG Download and Test Tool for an SOI-Based FPGA
Yan Li, Stanley L. Chen, Guoquan Zhang · ASME Press eBooks · 2011
An integrated download and test tool based on IEEE 1149.1 JTAG methodology is designed for use in downloading and testing an SRAM-based FPGA chip. The chip is fabricated with a 0.5um SOI-CMOS process technology. Comparing with Xilinx FPGA configuration tool iMPACT, our integrated tool adds a full range of test capabilities to the basic download functionality. This tool has been used in normal and radiation hardening tests of the fabricated chips and accomplishes a complete test set of high test coverage through both GUI and batch command modes.