Performance evaluation of the pipe computer architecture
Jian-Tu Hsieh · Minds at UW (University of Wisconsin) · 1986
PIPE (Parallel Instruction and Pipelined Execution) is a high performance computer architecture with several features that make it well-suited for VLSI implementation. Special implementation features of the PIPE processor include an instruction cache and a pipelined implementation of both the instruction unit and the ALU. Special architectural features of PIPE include the architectural queues and the decoupled mode of execution. The goal of this study is to evaluate the performance of a PIPE computer system. We implemented a detailed, trace-driven performance simulator and a probabilistic model of the PIPE system for this study. Extensive simulation results on a set of hand-coded benchmarks are presented and analyzed. Various parameters and execution modes of the PIPE architecture are used in the simulation. Usefulness of architectural queues and decoupled architectures is demonstrated by the simulation results. Dependence of PIPE's performance on program characteristics, hardware speed, and system configuration is studied. We also investigate optimizing techniques suitable for the PIPE architecture and demonstrate them by examples. The simulator and the simulation results of this study can be used to guide the efforts in hardware implementation and software development for the PIPE architecture.