An Evolvable-Hardware-based clock timing architecture towards GigaHz digital systems
Eiichi Takahashi, Masahiro Murakawa, Kenji Toda, Tetsuya Higuchi · 1999
There are increasing demands for high-speed LSIs such as Pentium III(500 MHz) and DEC Alpha (600MHz). However, these fast digital systems have poor yield rates. In early stages of mass production of such LSIs, it is believed that yield rates might be less than 10 %. One of the reasons for poor yield rates is that the timing delays between digital components are not the same as the design specifications. Such discrepancy comes from the variations in the values of parasitic capacitances and resistors along data lines between digital components. Those values differ significantly depending on LSIs. The LSIs that do not satisfy the design specifications are just discarded, leading to poor yields rates. In order to solve this problem, we propose an EHW (Evolvable Hardware)-based clock architecture for high speed digital systems. In stead of just discarding the chips that do not meet the specifications, we genetically adjust the clock timings in the LSI and let it satisfy the specifications. We have developed a LSI, which is used in the high-speed memory tester, to show the advantages of the clock architecture. Simulation results show that the number of LSIs which can operate at 800 MHz increases from 2.9% to 51.1% after the clock timing circuits are evolved by genetic algorithms. Therefore, this clock architecture is expected to be one of the basic LSI technologies for GigaHz digital systems.