Design Tradeoffs for Embedded Network Processors
Wolf, Tilman · Open Scholarship Institutional Repository (Washington University in St. Louis) · 2000
Demands for flexible processing has moved general-purpose processing into the data path of networks. With the development of System-On-a-Chip technology, it is possible to put several processors with memory and I/O components on a single ASIC. We present a model of such a system with a simple performance metric and show how the number of processors and cache sizes can be optimized for a given workload. Based on a telecommunications benchmark we show the results of such an optimization and discuss how specialied hardware and appropriate scheduling can further improve system performance.