Estimating Logic Cell to I/O Pad Lengths in Computer Systems
Dirk Stroobandt, Herwig G. Van Marck, Jan Van Campenhout · Ghent University Academic Bibliography (Ghent University) · 1997
Increasing system complexity imposes high demands on computer aided design (CAD) tools for system synthesis. Especially the layout (placement and routing) of a design has become a problem hard to solve. To find a `good' layout, CAD tools need accurate estimators to predict area requirements, interconnection lengths, power dissipation, etc. In this paper we address the estimation of interconnection lengths. Previous work on this subject is primarily based on a technique introduced by Donath [1] which has been improved by Stroobandt et al [2]. However, this technique only estimates interconnection lengths between two cells within the system or chip. Of equal importance to the CAD tools is the length estimation of interconnections between cells and I/O pads. This paper provides a technique to accurately estimate cell to I/O pad lengths. I. Introduction The production of VLSI and ULSI computer chips requires the layout (placement and routing) of the chip design on a carrier. With the adve...