Realization of Generalized Parallel Counter for Improving FPGA Performance
S. Deivasigamani, G. Narmadha, K. Balasubadra · ASME Press eBooks · 2011
In this paper, we proposed that the selective use of carry-save arithmetic can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP applications whereas Field-programmable gate-arrays (FPGAs), however, are not particularly well suited to carry-save arithmetic. To address this concern, we introduce the 1œField Programmable Counter Array 1(FPCA), an accelerator for carry-save arithmetic intended for integration into an FPGA. And this FPCA can be built by using Generalized Parallel Counter (GPC). The proposed GPC reduces the complexity of carry-save arithmetic compared to basic adders.