On CMOS totally self-checking circuits
Sridhar R. Manthani, Sudhakar M. Reddy · International Test Conference · 1984
To model faults in CMOS VLSI digital circuits, an augmented fault model comprising FET stuck-open and stuck-on faults, in addition to line stuck-at faults, is being used. Recently, it was discovered that delays in CMOS circuits under test. could invalidate tests derived by neglecting such delays. Thus, it is necessary to reinvestigate most of the existing design and test methods which are based on stuck-at fault models while considering CMOS digital circuits. One of the areas that requires such a revisit is that of self-checking circuits, due to the fact that the self-testing property of these circuits is dependent upon fault model adopted. In this paper, the problem of the design of CMOS totally self-checking checkers is considered when arbitrary delays in the circuit under test are allowed. Designs using both full CMOS and domino gates are considered. Several design procedures given earlier for totally self-checking checkers are analyzed under the augmented fault model. Adequate design rules are derived for some of the checkers, such that the self-testing property is retained for the augmented fault model.