A multiprocessor data flow accelerator module
George S. Davidson, P. Pierce · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 1988
Real-time controllers often need to minimize the latency between the arrival of a stimulus and the delivery of a control signal. Using multiprocessors to compute the control algorithm is appealing for these applications, but problem decomposition and load leveling are not straightforward. The data flow model of computation offers a solution which can be implemented for shared memory, parallel processors by the addition of a single circuit board. A typical parallel processor, the data flow model, and several versions of the Data flow Accelerator Module (DFAM) are presented together with some preliminary results. 15 refs., 12 figs.