Programming Architectures For Run-Time Reconfigurable Systems
Katherine Compton · 2000
Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. By mapping the compute-intensive sections of an application to reconfigurable hardware, custom computing systems exhibit significant speedups over traditional microprocessors. However, the number and frequency of these hardware-mapped sections of code are limited by the requirement that the speedups provided must outweigh the considerable time cost of configuration. The ability to relocate and defragment configurations on an FPGA can dramatically decrease the overall configuration overhead incurred by the use of the reconfigurable hardware. This increases the viability of mapping portions of the program that were previously considered to be too costly. We therefore explore the adaptation of a simplified Xilinx 6200 series FPGA for relocation and defragmentation. Because of the complexities involved with this structure, we also present a novel architecture designed from the ground up to provide relocation and defragmentation support with a negligible area increase over a generic partially reconfigurable FPGA.