Integration of existing optimisation techniques with the DWARV C-to-VHDL compiler
M. Slotema · Research Repository (Delft University of Technology) · 2012
Hardware acceleration using recon?gurable devices is a hot research item. To facilitate this acceleration technique, also called recon?gurable computing, tools are being developed that translate High-Level Languages into Hardware Description Languages. DWARV is such a tool developed at Delft University of Technology, translating C into VHDL. The way C code is written a?ects the performance of DWARV signi?cantly. Manual modi?cations can improve the speedup of that kernel signi?cantly. This thesis will work towards closing the performance gap between modi?ed sources and unmodi?ed sources. By integrating di?erent optimisation techniques, less manual modi?cations will need to be made for improved performance. The techniques covered by this thesis are loop unrolling, loop invariant code motion, software-sided caching and algebraic simpli?cations. Integrating these techniques into DWARV was done, taking into account possible dependencies between the di?erent optimisation techniques. When combining all these techniques together, speedups of 2.8 were achieved for individual kernels. On average, a kernel is 1.45 times faster when the optimisation techniques from this thesis are used.