An Automatic Generation of Shared Bus RTL Model from Transaction Level System Specification
Kwanhu Bang, Dong Seong Kim, Eui-Young Chung · 2007
In recent complex System-on-Chip(SoC) design, high level system modeling techniques such as Transaction-Level Modeling(TLM) are widely used for fast simulation and verification. The advantage of TLM methods is the fast simulation speed, hence it is appropriate for the ex ploration of a large design space. However, it is commonly observed that the TLM is not automatically translated into the RTL specification. In other wo rds, the advantage of TLM is depreciated by the manual translation due to the time for the coding and verification in RTL design stage. This paper proposes an automatic generation of synthesizable shared bus RTL model, from the system specification simulated and verified with TLM design. The technique enables fast system design and synthesis only with high level simulation and verification. The experimental result shows that the simulation time of TLM is about 50 times faster than that of RTL model, and the modeling effort of TLM also reduced significantly. I. 서론