Reverse engineering of real PCB level design using VERILOG HDL
Nikolaos Bourbakis, V. J. Gallardo, C Koutsougeras · International journal of engineering intelligent systems for electrical engineering and communications · 2002
The repair or replacement of components nearing obsolescence and the lack of accuracy in technical information is a very common problem. Updating these systems is possible now with sophisticated CAE tools and the Hardware Description Languages. Here we consider the conversion process of a real board design from TTL implementation to newer technology. This process is performed through an Automatic Verilog HDL Model Generator, which includes an image analysis system, for component identification(integrated circuits) and their connections. On the basis of the information obtained, the system is able to generate a circuit graph that corresponds to a primitive schematic circuit of the board. The circuit graph is translated to VERILOG HDL. The tests were performed in Verilog XL simulator. Therefore the system is capable to reverse engineer a board level design performed with a nondestructive procedure.