A Rule-Based Software Testing Method for VHDL Models.
Anneliese Amschler Andrews, Andrew O'Fallon, Tom Chen · 2003
The verification of behavioral models is an important step before transferring a hardware design to the layout. A popular approach is to use a variety of code coverage measures to evaluate how much of the design has been simulated. Common coverage measures include branch coverage and bit toggle coverage. This paper presents a test pattern generation approach based on controlflow and dataflow analysis. Heuristic rules use the results of the static analysis to generate new patterns. We applied this technique to a sizable VHDL design and compared resulting coverage to other methods. The results showed that this new method achieved higher branch coverage. 1.