VLSI layout of Benes networks
Paul D Manuel, Kalim Qureshi, Albert William, Albert Muthumalai · Journal of Discrete Mathematical Sciences and Cryptography · 2007
The Benes network consists of back-to-back butterflies. There exist a number of topological representations that are used to describe butterfly–like architectures. We identify a new topological representation of Benes network. The significance of this representation is demonstrated by solving two problems, one related to VLSI layout and the other related to robotics. An important VLSI layout network problem is to produce the smallest possible grid area for realizing a given network. We propose an elegant VLSI layout of r-dimensional Benes networks using this representation. The area of this layout is O(22r ) whereas the lower bound for the area of the VLSI layout of Benes networks is O(22r ). This lower bound is estimated by applying Thompson result.