Performance of Parallel Hash Hardware with Key Deletion.
Tetsuo Ida, Eiichi Goto · Institutional Repositories DataBase (IRDB) · 1977
Hash hardware is proposed which can handle key deletion without key relocations. It makes use of parallelism of memory accesses and can be realized by conventional multi-bank memory with additional logic circuitry. Three parallel hash algorithms to be implemented in the hardware are described and their efficiencies are compared. The amount of additional logic varies, depending upon the algorithm to be used and upon a scheme for handling inactive key positions. The result of the analysis shows that basic hash operations can be performed in the time comparable to single indirect addressing.