The First Clock Cycle Is A Real BIST.
Charles E. Stroud, Bradley F. Dutton · 2010
The primary goal of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) is to comple tely test all programmable logic and routing resources i n the device such that the user can be assured that their system function is downloaded to a fault-free device. In this paper, we present case studies of developing BIST configur ations for some of the less thought of, though equally imp ortant, logic resources in current FPGAs including programm able clock buffers and cyclic redundancy code (CRC) modu les. While seemingly trivial, these modules present inte resting testing challenges in FPGAs. Among the most intere sting challenges are the problems, and importance, associ ated with the very first clock cycle of the BIST sequenc e when testing FPGA initialization capabilities, or lack tvia the configuration download. While the conditions m ay last for only one clock cycle, testing these features is essential to insure the intended system function is properly ini tialized during operation. 1