A Non-Uniform Cache Architecture on Networks-on-Chip: A Fully Associative Approach with Pre-Promotion
Akio Kodama, Toshinori Sato · 2004
Global interconnect becomes the delay bottleneck in microprocessor designs, and latency for large on-chip caches will be intolerable in deep submicron technologies. The recently-proposed Non-Uniform Cache Architectures (NUCAs) exploit the variation in access time across subarrays to reduce typical latency. In the dynamic NUCA (D-NUCA) design, a set-associative structure is selected and thus the flexibility of data placement and replacement is limited. This paper investigates one of the unexplored design space; a fully as-sociative approach. In addition, we propose a pre-promotion tech-nique to reduce the number of incremental search in the distributed cache banks. We show that, compared with a traditional multi-level cache, up to 110 % improvement in IPC is achieved at 30nm. 1