Easily testable interconnection network from three-state cells (parallel processing)
Sung-chun Kim, Dharma Prakash Agrawal · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 1983
A design methodology for an easily testable multistage interconnection network utilising three-state switching elements (SES) is presented. The proposed network topology is determined from a general graph model of such networks. The network is implemented in such a way that one test is enough to detect single or multiple faults. The faculty modules are tested and reflected at the output of the external links. Such modules consist of a large number of 2-input/2-output three-state SES and are assumed to be fabricated with LSI/VLSI technology. 16 references.