HIGH PERFORMANCE SCALABLE RADIX-2n GF(2m) SERIAL–SERIAL MULTIPLIERS
ABDURAZZAG SULAIMAN ALMILADI, MOHAMAD IBRAHIM · Journal of Circuits Systems and Computers · 2009
In this paper, a new architecture for radix-2n serial–serial multiplication/reduction for the finite field GF(2m) is presented. The input operands are serially entered one digit at a time and the output result is computed serially one digit at a time. The reduction polynomial is also fed serially to the structure so that changing the reduction polynomial will not require rewriting or rewiring the structure. The structure utilizes a serial transfer which reduces the bus width needed to transfer data back and forth between memory and multiplication unit. The structure possesses features of regularity, modularity and scalability which are a design requirement for an efficient utilization of FPGA resources. Also, a systolic scalable area efficient design which provides a 50% reduction in hardware without degrading the speed performance is proposed. A radix-4 version of the proposed architecture has been designed, simulated and synthesized using Xilinx ISE 10.1 targeting a Xilinx Virtex-5 FPGA.