The HPEC Challenge Benchmark Suite
Ryan Haney, Jeremy Kepner · 2006
Quantitative evaluation of different multi-processor High Performance Embedded Computing (HPEC) systems is an ongoing challenge for the HPEC community. The DARPA Polymorphous Computer Architecture (PCA) and HighProductivity Computing Systems (HPCS) programs have created kernel and system level benchmarks and metrics for comparing the different architectures being developed under these programs. In this talk, we will describe a new benchmark suite drawn from the HPCS and PCA programs: the HPEC Challenge Benchmarks. It consists of eight single-processor kernel benchmarks and of a multiprocessor scalable synthetic SAR benchmark. We describe an implementation of the kernel benchmarks on the PowerPC G4 and the metrics used to evaluate it. We also demonstrate the parallel SAR benchmark and its scaling to multiple problem and machine sizes. The HPEC Challenge suite will be made widely available to community and will enable more rigorous comparison of HPEC systems.