Implementation of the Sign-Logarithm Arithmetic FFT,
S. J. Kidd, Malvern (UK) Royal Signals and Radar Estabslihment · Defense Technical Information Center (DTIC) · 1983
The simulation studies described show that sign-logarithm arithmetic can be implemented in a practical digital fast fourier transforms (FFT) analyser. Sign-logarithm arithmetic allows a smaller wordlength than conventional fixed point arithmetic whilst maintaining performance. Discussion of the hardware implementation of such a sign-logarithm FFT shows that power consumption can be less than conventional methods using bipolar multipliers. The use of a smaller wordlength allows a significant simplification of the system into which the FFT is placed and a higher data throughput rate. (Author)