Design representation and behavioral transformation for algorithmic level integrated circuit design
Robert A. Walker · 1988
Now that the field of automated synthesis for register transfer level integrated circuit design is beginning to mature, it is appropriate to begin developing tools for higher levels of design. At the next higher level, it is appropriate to explore behavioral and structural partitioning, answering such questions about the design as: (1) Should the behavior be implemented on a single VLSI chip, or should it be split across two or more chips? (2) Should the behavior be implemented as a single process, which a single data path and controller, or should it be split into two or more processes, each hopefully smaller and faster than the single process design, and with more potential concurrency? (3) Should the behavior be pipelined or left unpipelined, and if it is to be pipelined, how many stage divisions should there be, and where should they be placed? It has been the goal of this research to define the Algorithmic Level of design (also known as the Behavioral Level) and to provide the designer with the means to explore these issues. Within the framework of the System Architect's Workbench, a model of design representation was developed to represent and coordinate the behavioral, structural, and physical information, and a new set of behavioral and structural transformations was developed to allow the exploration of high-level design alternatives. Both this model and the transformations are described in this dissertation. A set of examples are also presented, both to demonstrate the application of the transformations, as well as to further characterize their effects.