Testability analysis of MOS VLSI circuits
David M. Singer · International Test Conference · 1984
Modeling problems that are encountered in applying an existing testability measure to MOS circuits are identified. These problems arise primarily because MOS circuits can implement functions that cannot be modeled at the logic gate level. Models for the testability analysis of circuits with memories (RAM and ROM), buses, and transmission gates are developed. In addition, the use of the controllability/observability measures in analyzing the testability of stuck-at-faults, and in defining an overall circuit testability index is discussed.