High-speed lattice wave digital filters for interpolation and decimation
Håkan Johansson, Kent Palmkvist, Mark Vesterbacka, Lars Wanhammar · 1996
Bit-serial arithmetic is often advantageous both in terms of small chip area and low power consumption. When using bit-serial arithmetic for implementation of recursive digital filters, the maximal sample frequency is inversely proportional to the coefficient word lengths of the filters. For high-speed applications it is therefore essential to find filter structures with short coefficients. One way to do this is to use cascaded low-order filters instead of one high-order filter. Problems arise though when the cascaded filters are to be used for interpolation and decimation, since the straightforward realization increases the workload due to the different sample rates involved. However, we have developed a novel realization technique which keep the workload at a minimum with the additional possibility to use a high sample frequency. A digital filter for both interpolation and decimation, realized using this novel technique applied on two cascaded lattice wave digital filters, has been implemented. The filter can be used for sample rate conversions between 25 and 50 MHz.