Fast Redundancy Elimination Using High-Level Structural Information from Esterel
Dumitru Potop‐Butucaru · OpenGrey (Institut de l'Information Scientifique et Technique) · 2001
Esterel programs and SyncCharts hierarchical automata are compiled into flat sequential circuits. The current compiling process often generates too many latches and gates. We propose a compositional technique based on structural information that efficiently removes redundant latches and gates, without adding extra logic. The transformation works in linear time and gives good practical results. The simplified circuit can be used for simulation, verification, and optimisation.