Efficient parallel simulation for designing multiprocessor systems.
Jia-Jen Lin · Deep Blue (University of Michigan) · 1992
Simulation has emerged as the primary means for evaluating the design of multiprocessor systems. Simulation of such systems has become increasingly time-consuming because of the increasing complexity of the interactions between components of the systems and the need to simulate large parallel programs to obtain accurate performance prediction. The objective of this thesis is to develop fast efficient simulation techniques that can reduce simulation time sufficiently so that the performance of large parallel programs can be examined in a reasonable time. Such techniques when incorporated in simulation tools will reduce design time, improve multiprocessor designs, and enable the concurrent development of optimized multiprocessor software. SIMPLE (Simulation Instrument for Multiprocessors at Program Level using Emulation), a software package for simulating multiprocessor systems efficiently, uses high-resolution clocks on the host systems to directly obtain the timing of code-segments. SIMPLE automatically instruments parallel programs, directly executes the instrumented programs, and incorporates architecture parameters. SIMPLE usually takes no more than 2 instructions to simulate 1 instruction, compared to 300 or more for accurate instruction-level simulators. Techniques were developed to parallelize multiprocessor simulators. The importance of dynamic topological information and global simulation information was identified, and the DLC (Dynamic Logical Channel) and DAI (Direct Access of Information) schemes were developed to exploit this information. In the DLC scheme, parallel programs are analyzed and instrumented before simulation. During simulation, information on the interactions between execution threads in gathered. By exploiting this information, the set of possible interactions is limited and simulation parallelism is improved. The DAI scheme aggressively collects useful simulation information in shared-memory multiprocessor hosts to reduce nonessential blocking and resolve local deadlocks. The simulation overhead of collecting information is reduced by search-pruning techniques. The DLC and DAI schemes were used to parallelize SIMPLE. A prototype of parallel SIMPLE was constructed on the Sequent Symmetry multiprocessor.