HS-SCALE ADAPTIVE MPSOC PLATFORM
Gabriel Marchesan Almeida, Sameer Varyani, Gilles Sassatelli · 2009
Multiprocessor Systems on Chip (MPSoCs) are becoming increasingly popular as they provide a very flexible and reusable platform for parallel processing. Several challenges however arise, such as system reliability, scalability, adaptability, etc. Generally, embedded systems, such as mobile phones, are based on heterogeneous shared memory MPSoCs. Although this is the most popular architecture in practice, it does not allow any significant flexibility as tasks are statically mapped to processors at design time. The presented prototype system illustrates the research conducted at LIRMM in the area of homogeneous self-adaptive MPSoCs; it is constituted of an array of 16 processors connected through a packet-switching NoC. Each processor runs a dedicated microkernel capable of run time system analysis and taking corrective measures.