Analysis and performance evaluation of new architectures in high-speed packet switching
Christos Kolias, Leonard Kleinrock · 1999
ATM switching is recognized as an ultra-fast packet switching and asynchronous multiplexing technology. Its merits stem from the use of fixed-size packets called cells and its connection-oriented operation mode. We point out that all our techniques, designs and results presented have a broad scope and applicability in packet switching. The focus is on ATM switching since it has been the choice for implementing and deploying broadband, integrated- services networks. In this dissertation we propose, describe and evaluate a number of new packet switching architectures. Our objective is to provide high-performance, efficient but also low-complexity, cost-effective solutions. The starting point in our research is the input-queueing switch on which we propose a number of improvements in order to alleviate the Head-of-Line (HOL) blocking problem from which input-buffered switches suffer. The main idea is to employ multiple, parallel input queues per input port in order to segregate traffic destined for different outputs of the switch. This can lead to a significant enhancement of the switch's performance. Based on the multiple input-queueing technique we introduce the Odd-Even, the Multiple Input-Queueing (MIQ) and the Dual-Banyan multistage switches. Additionally, we describe and study two classes of switches with parallel switching planes. We also propose a switch that combines both speed-up and multiple input-queueing and can deliver the ideal performance. Lastly, we apply the power function in the context of ATM switching, which can been utilized as a performance evaluation and comparison tool. Our performance evaluation results are based on extensive analytical and simulation studies. The results are with reference to three metrics of our interest, namely throughput, mean delay and cell drop probability. Furthermore, we often compare our models to existing ones. At the end of this dissertation we study a number of queueing systems which provided us with the necessary tools in modeling our proposed architectures.