A systolic array for efficient matrix-matrix multiplication. [SPRINT]
Anthony J. De Groot, Erik M. Johansson, S. R. Parker · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 1987
The Systolic Processor with a Reconfigurable Interconnection Network of Transputers (SPRINT) is a sixty-four-processor multiprocessor developed at Lawrence Livermore National Laboratory for experimentally evaluating systolic algorithms and architectures. Its computation capabilities surpass its communication capabilities. Techniques have been developed to perform matrix-matrix multiplication utilizing most of its computing capability by operating on block matrices. These techniques reduce communication bandwidth requirements for a given computation rate. Using these techniques, processor efficiencies can approach 1. Previous techniques resulted in processor efficiency of 1/3. The algorithms are executed on the SPRINT to compare theory with experiment.