Performance and Programming Experience on the Tera MTA.
Larry Carter, John Feo, Allan Snavely · 1999
The Tera MTA (for "Multithreaded Architecture") computer features a radically new architecture, with hardware support for up to 128 threads per processor, a powerful instruction set, nearly uniform access time to all memory locations, and zero-cost synchronization and swapping between threads of control. Memory access latencies are tolerated by swapping between the threads. Given a multithreaded program with sufficient parallelism, the scalable memory system should allow uncommonly good scaling to multiple processors. This paper gives a brief description of the MTA's architecture and a few observations about its programmability, and then presents some performance figures. 1 The Tera MTA Each processor of the Tera MTA has 128 streams, where a stream is hardware that includes a program counter and set of 32 registers. Each stream can be assigned to (at most) one program thread. 1 A stream can issue one instruction, but then must wait at least 21 cycles (the length of the instruction p...