Integrated Digital Architecture for JPEG Image Compression
Luciano Volcan Agostini, Sérgio Bampi · 2001
This paper presents the architecture and design of a JPEG compressor in hardware. The system is a functional unit of a compressor chip, divided in four major parts: color space converter and downsampler, 2-D DCT module, quantization and entropy coding. Architectures for these four parts were designed and described in VHDL. The results of the VHDL mapping into Altera Flex 10K FPGAs are also herein presented.