Low Cost Techniques for High-Speed Implementation of Decision Feedback Equalizers for FPGAs
C. Papadopoulos · Research Repository (Delft University of Technology) · 2015
In modern digital communications throughput rates in the order of gigabits per second are not uncommon. Hence there is a need for fast equalizing filters. While all feed forward filters can easily be pipelined, therefore sped up, the feedback filter (FBF) of decision feedback equalizers is the bottleneck of its performance. A simple, extremely fast, reformulation of the FBF, based on an obvious expansion of the Shannon's expansion theorem idea, can easily be devised. This particular design can be retimed in a straightforward manner to reach its iteration period bound, but is ultimately limited by the propagation delay of the registers. Even though we can unfold the circuit in an attempt to limit the register's delay relevance, its hardware overhead is exponentially dependent on the number of tap coefficients (L), therefore, very costly even for relatively small Ls. In order to cope with the exponential area growth a two stage pre-computation schema, similar to the reformulated FBF, will be introduced. We show that the area degrades significantly with the penalty of decreasing the maximum achievable frequency. To reach its iteration bound, this new design has to be unfolded. In our experiments we use the Xilinx ISE FPGA synthesizer, targeting the Virtex 5 family, the XC5VLX20T module, set to speed -2. We will approximate the minimum needed unfolding factor for an FPGA centric design, considering different word lengths and number of tap coefficients, to use as a base for the experimental phase. Our experiments with the unfolding factor will conclude when the performance is comparable with that of the first FBF reformulation. For that final design we will find the L where the hardware overhead improvement outweighs the hit in performance. Finally, based on the experimental results, we will show that the performance can be further increased, with the introduction of a retime approach.