Comparison of SpecC and SystemC Languages for System Design
Lukai Cai, Shireesh Verma, Daniel D. Gajski · 2003
models Model aspect SystemC SpecC Specification model functional block module behavior schedule event, signal event, definition(par..) data transfer signal variable IP-assembly model structure blocks module behavior functional blocks process behavior schedule inside PEs event, signal event, definition(par..) schedule between PEs channel channel data transfer inside PEs signal variable data transfer between PEs channel channel Bus-arbitration model same as Arch model same as Arch model Bus-functional model same as Arch model same as Arch model Implementation model fsm switch(SC THREAD), SC CTHREAD fsmd function units function/module function/behavior storage variable signal buffered signal bus bit bit control signal signal signal Table 3. Overall comparison in terms of design modeling 23 scheduling using events and data transfer using variables without any constraint.