Multi processor system on chip platform and studying of the best architecture and software solution for an application
Francesco Poletti · AMS Dottorato Institutional Doctoral Theses Repository (University of Bologna) · 2007
Comparison of message passing implementations in a pipelined benchmark with 8 cores from Tab. 5.3 . . . . . . . . . . . . . . .5.5 Task scheduling impact on synchronization in a pipelined benchmark with 4 cores from Tab. 5.3 . . . . . . . . . . . . . . . . . . .5.6 Exploration Space.Within each space partition, other software parameters have been explored such as data locality, computation/communication ratio and data granularity. . . . . . . . . . . . . . . . . . . . . . . . .5.7 Workload allocation policies for parallel matrix multiplication. .5.8 Workload allocation policy for DES encryption algorithm (up) and signal processing pipeline (bottom). . . . . . . . . . . . . . .5.9 Execution time ratio.D-cache size is a parameter.(a) MM benchmark.(b) synth-MM benchmark. . . . . . . . . . . . . . . . . . . . . . . .5.10 Throughput for the DES benchmark as a function of data granularity. .5.11 Energy for the DES benchmark as a function of data granularity. . . .5.12 Throughput for pipelined matrix processing.(a) Matrix multiplication.(b) Matrix addition. . . . . . . . . . . . . . . . . . . . . . . . . . . .5.13 Energy for pipelined matrix processing.(a) Matrix multiplication.(b) Matrix addition. . . . . . . . . . . . . . .