Sorting networks on FPGA
Devi Prasad, Mohamad Yusri Mohamad Yusof, Smruti Santosh Palai, Ahmad Hafez Nawi · International Conference on Signal Processing · 2011
Speed and efficiency of sorting algorithms are essential for high speed data processing. FPGA based hardware accelerators show better performance than the general purpose processors. Similarly traditional algorithms may not be always efficient on FPGAs. Sorting networks have come as suitable alternatives which can be implemented on FPGAs efficiently. Each application has its own constraint on latency and throughput. A careful selection of a sorting network with suitable number of pipeline stages performs at higher throughput, without contributing much latency.