A high-level synthesis based VLSI design methodology
Lawrence F. Arnstein · 1993
Though high-level synthesis tools seem to fit nicely into the traditional top-down VLSI design methodology in which an abstract algorithmic model is transformed into a detailed register transfer level implementation, there is an important difference between filling in the details by hand and relying on a high-level synthesis tool to do so. Unlike the hand-designer, an engineer who uses a synthesis tool is not likely to be familiar with the specific register transfer level implementation that is produced. Thus, the use of high-level synthesis tools can effectively inhibit the engineer's ability to attack design problems or make informed trade-offs at either the specification or implementation level. To enhance the potential for engineer involvement in the synthesis based design process we have developed a methodology that includes a new abstraction for modeling high-level synthesis specifications as well as results (called attributed-behavior), and a new high-level synthesis tool, based on binary constraint network and force-directed synthesis techniques, that accepts and produces models in this abstraction. In addition, we have constructed a framework to demonstrate the synthesis based design methodology that we envision, and to show its effectiveness in supporting an explorative design process characterized by increased cooperation between engineer and tool. Our re-formulation of the high-level synthesis task in terms of the attributed-behavior abstraction is described along with theoretical and practical results that are embodied in the new synthesis techniques. Two important experimental and practical results are presented. First, we show that the new synthesis tool can perform the traditionally defined high-level synthesis task with results that are as good or better than existing state-of-the-art traditional synthesis tools. We then demonstrate that the new attributed-behavior synthesis tool provides new capabilities that allow an engineer tool to attack design problems and make design trade-offs without circumventing the synthesis tool and without abdicating the high-level algorithmic perspective.