A METHODOLOGY FOR HARDWARE TASKS SCHEDULING OPTIMIZED IN TIME FOR PARTIAL AND DYNAMIC RECONFIGURATION OF FPGAS
Remy Eskinazi, Manoel Eusébio de Lima, Paulo Romero Martins Maciel, Carlos Alberto Valderrama, A.G.S. Filho, Paulo Sérgio B. Nascimento · Applied Reconfigurable Computing · 2005
Current high-end Field-Programmable-Gate-Array (FPGA) parts offer a large number of configurable resources. These can be organized in custom storage structures such as tapped-delay lines, in addition to a number of very dense highcapacity Random-Access-Memory (RAM) and Content-Addressable-Memory (CAM) blocks. The extreme flexibility of the size, organization and interconnection between these storage resources enables compilers to generate custom hardware designs tailored to capture the application-specific data reuse opportunities. In this paper we outline the basic compiler data dependence analyses approaches that can be used to uncover reuse opportunities within a loop nest. We then describe the challenges of exploiting these opportunities in modern FPGAs.