Low-power and Low-cost Design of Survival Memory Unit for 1000Base-T Gigabit Ethernet Transceiver
Zhu, Yue Yue, Rong, Meng-tian · 上海交通大学学报：英文版 · 2006
Types of hybrid architectures survivor memory unit (SMU) is presented,which are applicable to IEEE 802.3 ab 1000 Base-T Gigabit Ethernet (GbE) transceiver. Area, power and decoder latency were taken into account and most efficient architectures were compared to optimize area/power tradeoff in different kinds of applications. Suitable SMU architectures are given out respectively in area-restrict, power-restrict and latency-restrict designs. A power-efficient architecture was selected in our GbE project. It provides 48% improvement in area and 71% amelioration in power, compared to classical register exchange architecture (REA) SMU.